? semiconductor components industries, llc, 2009 august, 2009 ? rev. 0 1 publication order number: nb7v58m/d nb7v58m 1.8 v / 2.5 v / 3.3 v differential 2:1 clock / data multiplexer / translator with cml outputs multi ? level inputs w/ internal termination description the nb7v58m is a high performance dif ferential 2 ? to ? 1 clock or data multiplexer. the differential inputs incorporate internal 50 termination resistors that are accessed through the vt pin. this feature allows the nb7v58m to accept various logic level standards, such as lvpecl, cml or lvds. the nb7v58m produces minimal clock or data jitter operating up to 7 ghz or 10.7 gb/s, respectively. as such, the nb7v58m is ideal for sonet, gige, fiber channel, backplane and other clock/data distribution applications. the 16 ma differential cml outputs provide matching internal 50 terminations and 400 mv output swings when externally terminated with a 50 resistor to v cc . the nb7v58m is offered in a low profile 3 mm x 3 mm 16 ? pin qfn package and is a member of the gigacomm family of high performance clock / data products. for applications that require equalization, the pin ? compatible nb7vq58m is also available. application notes, models, and support documentation are available at www.onsemi.com . features ? maximum input data rate > 10.7 gb/s ? data dependent jitter < 10 ps ? maximum input clock frequency > 7 ghz ? random clock jitter < 0.8 ps rms ? 180 ps typical propagation delay ? 35 ps typical rise and fall times ? differential cml outputs, 400 mv peak ? to ? peak, typical ? operating range: v cc = 1.71 v to 3.6 v with gnd = 0 v ? internal 50 input termination resistors ? qfn ? 16 package, 3 mm x 3 mm ? ? 40 c to +85 c ambient operating temperature ? this is a pb ? free device a = assembly location l = wafer lot y = year w = work week = pb ? free package *for additional marking information, refer to application note and8002/d. marking diagram* qfn ? 16 mn suffix case 485g http://onsemi.com see detailed ordering and shipping information in the package dimensions sect ion on page 7 of this data sheet. ordering information 16 nb7v 58m alyw 1 simplified block diagram (note: microdot may be in either location) 1
nb7v58m http://onsemi.com 2 figure 1. pin configuration (top view) vt1 sel nc vcc vt0 gnd gnd q gnd gnd q in0 in0 in1 in1 5678 16 15 14 13 12 11 10 9 1 2 3 4 nb7v58m exposed pad (ep) vcc q q 0 1 2:1 mux vcc 25 k in0 in0 vt0 in1 in1 vt1 sel multi ? level inputs lvpecl, lvds, cml figure 2. detailed block diagram 50 50 50 50 table 1. select function truth table sel q q l in0 in0 h in1 in1 table 2. pin description pin name i/o description 1 in0 lvpecl, cml, lvds input noninverted differential input (note 1) 2 in0 lvpecl, cml, lvds input inverted differential input (note 1) 3 in1 lvpecl, cml, lvds input noninverted differential input (note 1) 4 in1 lvpecl, cml, lvds input inverted differential input (note 1) 5 vt1 ? internal 50 termination pin for in1/in1 6 sel lvttl/lvcmos input sel input. low for in0 inputs, high for in1 inputs. (note 1) pin will default high when left open (has internal pull ? up resistor) 7 nc no connect 8 vcc ? positive supply voltage (note 2) 9 q cml output inverted differential output 10 gnd ? negative supply voltage 11 gnd ? negative supply voltage 12 q cml output noninverted differential output 13 vcc ? positive supply voltage (note 2) 14 gnd ? negative supply voltage 15 gnd ? negative supply voltage 16 vt0 ? internal 50 termination pin for in0/in0 ? ep ? the exposed pad (ep) on the qfn ? 16 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is electrically connected to the die, and must be elec- trically and thermally connected to gnd on the pc board. 1. in the dif ferential configuration when the input termination pins (vt0, vt1) are connected to a common termination voltage or left open, and if no signal is applied on in0/in0 , in1/in1 inputs, then the device will be susceptible to self ? oscillation. q/q outputs have internal 50 source termination resistors. 2. all vcc and gnd pins must be externally connected to a power supply for proper operation.
nb7v58m http://onsemi.com 3 table 3. attributes characteristics value esd protection human body model machine model > 2 kv > 200 v r pu ? sel input pull ? up resistor 25 k moisture sensitivity (note 3) qfn ? 16 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 312 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 4.0 v v in positive input voltage gnd = 0 v ? 0.5 to v cc +0.5 v v inpp differential input voltage |inn ? inn | 1.89 v i out output current continuous surge 34 40 ma i in input current through r t (50 resistor) 40 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) 0 lfpm 500 lfpm qfn ? 16 qfn ? 16 42 35 c/w jc thermal resistance (junction ? to ? case) (note 4) qfn ? 16 4 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb7v58m http://onsemi.com 4 table 5. dc characteristics positive cml output (v cc = 1.71 v to 3.6 v; gnd = 0 v; t a = ? 40 c to 85 c) (note 5) symbol characteristic min typ max unit power supply current i cc power supply current (inputs and outputs open) 100 150 ma cml outputs (note 6) v oh output high voltage v cc = 3.3 v v cc = 2.5 v v cc = 1.8 v v cc ? 30 3270 2470 1770 v cc ? 5 3295 2495 1795 v cc 3300 2500 1800 mv v ol output low voltage v cc = 3.3 v v cc = 2.5 v v cc = 1.8 v v cc ? 500 2800 2000 1300 v cc ? 400 2900 2100 1400 v cc ? 300 3000 2200 1500 mv differential inputs driven single ? ended (note 7) (figures 6 & 8) v th input threshold reference voltage range (note 8) 1050 v cc ? 100 mv v ih single ? ended input high voltage v th + 100 v cc mv v il single ? ended input low voltage gnd v th ? 100 mv v ise single ? ended input voltage (v ih ? v il ) 200 1200 mv differential in0/in0 , in1/in1 , inputs driven differentially (figures 6 & 9) (note 9) v ihd differential input high voltage 1100 v cc mv v ild differential input low voltage gnd v cc ? 100 mv v id differential input voltage (v ihd ? v ild ) 100 1200 mv v cmr input common mode range (differential configuration, note 10) (fig- ure 10) 1050 v cc ? 50 mv i ih input high current (vtn open) ? 150 150 a i il input low current (vtn open) ? 150 150 a control input (sel) v ih input high voltage v cc x 0.65 v cc mv v il input low voltage gnd v cc x 0.35 mv i ih input high current ? 150 +150 a i il input low current ? 200 +200 a termination resistors r tin internal input termination resistor 45 50 55 r tout internal output termination resistor 45 50 55 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . 6. cml outputs loaded with 50 to v cc for proper operation. 7. vth, v ih , v il and v ise parameters must be complied with simultaneously. 8. vth is applied to the complementary input when operating in single ? ended mode. 9. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 10. v cmr min varies 1:1 with gnd, v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the differential input signal.
nb7v58m http://onsemi.com 5 table 6. ac characteristics (v cc = 1.71 v to 3.6 v; gnd = 0 v; t a = ? 40 c to 85 c) (note 11) symbol characteristic min typ max unit f max maximum input clock frequency voutpp 200 mv 7 8 ghz f datamax maximum operating data rate (prbs23) 10.7 12 gbps fsel maximum toggle frequency, sel 25 50 mhz v outpp output voltage amplitude (@ v inppmin ) (note 12) (figures 8 & 10) f in 7 ghz 200 400 mv t plh , t phl propagation delay to differential outputs, @ 1 ghz, measured at differential cross ? point inn/inn to q, q sel to q, q 120 5 180 13 240 22 ps ns t plh tc propagation delay temperature coefficient 50 f s/ c t skew device ? device skew (tpdmax ? tpdmin) 50 ps t dc output clock duty cycle (reference duty cycle = 50%) f in 5.0 ghz f in 7.0 ghz 45 40 50 50 55 60 % t jitter rj ? output random jitter (note 13) dj ? residual output deterministic jitter (note 14) f in 7.0 ghz f in 10.7 gbps 0.2 0.8 10 ps rms ps pk ? pk n phase noise, f c = 1 ghz 10 khz 100 khz 1 mhz 10 mhz 20 mhz 40 mhz ? 135 ? 136 ? 150 ? 151 ? 151 ? 151 dbc t n integrated phase jitter (figure 4) f c = 1 ghz, 12 khz ? 20 mhz offset (rms) 35 fs crosstalk induced jitter (adjacent channel) (note 15) 0.7 ps rms v inpp input voltage swing (differential configuration) (figure 10) (note 16) 100 1200 mv t r , t f output rise/fall times @ 1 ghz (20% ? 80%) q, q 15 35 50 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. measured using a v inpp min source, 50% duty cycle clock source. all output loading with external 50 to v cc . input edge rates 40 ps (20% ? 80%). 12. output voltage swing is a single ? ended measurement operating in differential mode. 13. additive rms jitter with 50% duty cycle clock signal. 14. additive peak ? to ? peak data dependent jitter with input nrz data at prbs23 at 3 gbps. 15. crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the inputs. 16. input voltage swing is a single ? ended measurement operating in differential mode. figure 3. output voltage amplitude (v outpp ) vs. input frequency (f in ) at ambient temperature (typical) f in , clock input frequency (ghz) 8 7 5 4 3 2 1 0 200 250 300 350 400 450 500 v outpp , output voltage amplitude (mv) 69 figure 4. typical phase noise (v cc = 1.8 v, t = 25 c, f c = 1 ghz) 10 ? 155 ? 150 ? 145 ? 140 ? 135 ? 130 ? 125 ? 120 ? 11 5 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+0 8 frequency offset (hz) power (dbc)
nb7v58m http://onsemi.com 6 figure 5. input structure 50 50 v cc inn inn i vtn in v th in v th figure 6. differential input driven single ? ended v ih v il v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin gnd v th figure 7. differential inputs driven differentially in in figure 8. v th diagram v ildmax v ihdmax v ihdtyp v ildtyp v ihdmin v ildmin v cmr gnd v id = v ihd ? v ild v cc in in q q t plh t phl v outpp = v oh (q) ? v ol (q) v inpp = v ih (in) ? v il (in ) figure 9. vid ? differential inputs driven differentially figure 10. v cmr diagram figure 11. ac reference measurement v ihd v ild v id = |v ihd(in) ? v ild(in )| in in v cmrmax v cmrmin in in
nb7v58m http://onsemi.com 7 lvpecl driver v cc gnd z o = 50 v t = v cc ? 2 v z o = 50 nb7v58m in x 50 50 in x gnd figure 12. lvpecl interface lvds driver v cc gnd z o = 50 z o = 50 nb7v58m 50 50 gnd figure 13. lvds interface v cc v cc figure 14. standard 50 load cml interface figure 15. capacitor ? coupled differential interface (v t connected to external v refac ) *v refac bypassed to ground with 0.01 f capacitor in x in x v t = open cml driver v cc gnd z o = 50 z o = 50 nb7v58m 50 50 gnd v cc in x in x v t = v cc differential driver v cc gnd z o = 50 z o = 50 nb7v58m 50 50 gnd v cc in x in x v t = v refac * figure 16. typical cml output structure and termination v cc 50 50 16 ma 50 50 v cc (receiver) gnd nb7v58m receiver q q (see application note and8173) ordering information device package shipping ? nb7v58mmng qfn ? 16 (pb ? free) 123 units / rail NB7V58MMNHTBG qfn ? 16 (pb ? free) 100 / tape & reel nb7v58mmntxg qfn ? 16 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb7v58m http://onsemi.com 8 package dimensions 16 pin qfn case 485g ? 01 issue d 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ l1 detail a l alternate terminal constructions ?? 0.00 0.15 mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hol d scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb7v58m/d gigacomm is a trademark of semiconductor component industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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